Module, Fab and Enterprise. The Module tier covers APC, defect or virtual-metrology AI on one process module or tool fleet. Fab covers the whole loop and the twin. Enterprise is for multi-fab IDMs and foundries. Annual prepay carries a 15 to 20% discount and outcome components are available on yield-point value, excursions and cycle time.
Floor pricing is protected. Discounts are traded for term length and a reference where IP allows.
Land on one workflow with a measured baseline. Expand by module, tool fleet, fab and autonomy level. Outcome components are available on yield-point value, excursions and cycle time. Annual prepay carries a 15 to 20% discount.
APC, defect or virtual-metrology AI for one module: litho, etch, deposition or CMP. For fabs validating ROI on the wedge, IP-isolated from day one.
The whole loop: litho and overlay, etch and deposition, CMP and implant, clean and diffuse, defect, metrology and virtual, yield and dispatch, AMHS and the fab twin.
Multi-fab IDMs and foundries standardising on Waferira, with custom process, device and yield models and a managed fab-edge fleet.
Products are licensed per module or tool fleet on the Module tier and bundled on Fab and Enterprise.
| Capability | Module | Fab | Enterprise |
|---|---|---|---|
| Modules covered | 1 | All in the fab | All fabs in the group |
| Agents | 1 of 5 products | All agents | All agents + custom models |
| As-run fab twin (Fabtwin) | No | Included | Custom process and flow models |
| Fab-edge node | Included | Per module | Fleet managed |
| Bounded recipe writes | Qualified window, one module | All qualified windows | Group policy |
| Wafer and lot genealogy | Included | Included | Included + export |
| Autonomy levels | L1 to L2 | L1 to L3 | L1 to L4 on qualified loops |
| SSO and RBAC | No | Planned | Planned, with approval chains |
| On-prem control plane | No | Optional | Included |
| Support | Business hours | 24/7 | 24/7 + named engineer |
| Indicative price | $30,000/mo | $220,000/mo | $2M to $20M ACV |
We do not publish savings percentages because we have not measured any yet. These are the inputs a fab brings to the pilot baseline, and the outputs the pilot measures.
A run engine that produces this record on every lot, every shift, on every module you license.
Fab Orchestrator · Pulled lot L-48213 from fab MES: 25 wafers, 300 mm, metal-1 layer, route, reticle, overlay and CD spec and the standing cycle-time target. Locked the target envelope for the run.
Fab Twin · Simulated 64 candidate correctable, recipe and dispatch sets on the as-run fab twin and ranked them on predicted overlay residual, CD uniformity, excursion risk and cycle time.
Litho-and-Overlay · Per-field overlay correctables and a focus-dose trim written to scanner SCN-07 over SECS/GEM after the previous lot's residual trended toward the control limit. Predicted overlay residual back inside spec.
Etch-and-Depo · Chamber B on etcher ETCH-12 showed an edge-fast uniformity drift in FDC. Pressure and RF trims written within the qualified recipe window; predicted CD uniformity recovered.
CMP-and-Implant · Downforce and platen-speed trim on CMP-03 against the virtual removal-rate estimate to hold post-CMP thickness and dishing inside the window.
Defect-and-Inspect · Inline optical, e-beam review and SEM imagery fused at the tool edge. 1,412 events classified, most dispositioned nuisance; one reticle-repeater signature on three dies flagged for review.
Metrology-and-Virtual · Virtual metrology scored every wafer at post-etch and post-CMP from tool-sensor and FDC signatures. Two wafers routed to physical metrology on predicted variance; the rest sampled at plan.
Fab Orchestrator · The reticle-repeater signature called for a reticle inspection hold and a recipe move outside the qualified window. Held for the module process engineer and approved at 03:14:27.
Yield-and-Dispatch · Dispatch re-optimised across 1,840 lots in WIP under reticle, chamber and qualification constraints. The lot routed to the qualified chamber with the shortest predicted queue; AMHS move issued to the stocker.
Quality-and-Conformance · Lot L-48213 moved on: genealogy written (recipe moves, correctables, FDC signatures, VM scores, defect map, approvals) and checked against the layer spec.
Logic and foundry, memory, analog and mixed-signal, specialty and compound semiconductor, and new fabs ramping a node. Most fabs pick one module and one wedge, prove the number, then expand.
Sub-3 nm, gate-all-around and backside-power nodes where overlay and CD budgets decide yield. Lithera and Vmetra on the litho and etch modules first.
High-aspect-ratio etch and deposition uniformity and CMP planarisation on long flows. Vmetra and Scanira where excursions are most expensive.
Many products, many recipes, few engineers per tool. Virtual metrology and defect disposition to cover more wafers with the same team.
SiC, GaN and photonics fabs with their own defect and uniformity physics. Scanira and Vmetra models trained per process family.
Reshored and greenfield capacity ramping under schedule pressure. Fabtwin de-risks the ramp before lots run.
Waferira writes to production tools over SECS/GEM. Every capability is scoped to a qualified recipe window, every write is policy-checked against tool state, and every action is written to an append-only, IP-isolated audit log the fab owns.
| Item | Scope | Status |
|---|---|---|
| SOC 2 Type I and fab-security review | Control plane | QUEUED Planned, first 6 months |
| SOC 2 Type II | Control plane | QUEUED Planned, 6 to 12 months |
| SSO and RBAC | Console and approvals | QUEUED Planned, 6 to 12 months |
| IP-isolation and security assurance package | Fab security and IT and OT review | QUEUED Planned, 6 to 12 months |
| SEMI-standards-cited reasoning | Recipes, integration specs, OCAPs | RUNNING In the design, every answer cites its source |
| Per-tenant IP isolation | Data, models, memory | RUNNING In the design from day one |
| On-prem and fab-edge deployment | IP-sensitive fabs | RUNNING Design option |
One policy model, one audit trail, one benchmark across every module in every fab, with the process, device and yield models kept private to each site.
The questions fab directors and process engineers ask in the first meeting.
Yes, over SECS/GEM, but only inside the qualified recipe window for that tool, with per-parameter limits and tool-state checks, and only at the autonomy level your fab has set. Level 1 is advisory: Waferira recommends and an engineer enters everything. Design partners start there, in shadow mode.
The tool stays on its own controller and its last qualified recipe. Waferira is a supervisory layer on top of the APC, inspection, metrology and MES systems you already run, never a replacement for them, so an outage leaves the module running the way it runs today.
No. Inference and feature storage stay at the fab edge, recipes, device designs, defect libraries and process memory are isolated per tenant, and an on-prem control plane is available for IP-sensitive fabs. Any cross-fab learning is planned, contract-gated and privacy-preserving, and none of it moves recipes or designs.
Advisory recommendations start from the existing APC, metrology and ADC data on the wedge module. Defect classification, virtual metrology and excursion prediction improve as labelled events and lot outcomes accumulate per process family. Rare excursions are augmented synthetically only after validation against real distributions.
You are, the same as with any APC strategy, which is why every write is policy-checked, bounded to the qualified window, logged and reversible, and why holds, out-of-window moves and lot release wait for a named approver with the OCAP linked.
A paid pilot on one process module or tool fleet, scoped to one wedge workflow with a baseline agreed in writing. Shadow mode first, observing and measuring the baseline. Then assist mode, where the agent recommends and your engineer approves and accuracy and ROI are measured. Then bounded autonomy for low-risk APC, defect or metrology loops if the fab is satisfied.
Start with one process module or tool fleet and one measurable baseline. A paid, IP-isolated pilot on defect classification, virtual-metrology-driven overlay and CD control or uniformity APC shows the number before you commit further.
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