Customers

Who we build for, and who we are looking for first.

Waferira is pre-launch. We have no customers to name and will not borrow logos. This page says who the product is for, what a design partner commits to, and who we deliberately do not target.

Pre-launch2 to 4 design partnersPaid pilot on one module

Ideal customer

Semiconductor front-end manufacturers, $1B to $100B+ revenue

Logic and foundry, memory (DRAM, NAND, HBM), analog and mixed-signal, and specialty and compound-semiconductor IDMs and foundries running litho, etch, deposition, CMP, implant, diffusion, clean and metrology and inspection modules.

lithoetch and depositionCMPinspectionmetrologyMES
Qualification

What makes a good first fab

The criteria we check, in order.

We look for

  • Sufficient wafer volume, value and yield stakes to drive a clear ROI
  • Existing APC, defect-inspection, metrology and MES systems with SECS/GEM tool integration for connectivity
  • An executive mandate to raise yield or cut excursions, cycle time or cost per wafer and automate process control
  • Willingness to run an IP-isolated paid pilot with a defined yield, excursion or cycle-time success metric

We do not target

  • Pure test, assembly or packaging houses with no front-end wafer scope
  • Sites unwilling to integrate APC, defect, metrology, MES and tools under strict IP and security controls
  • Buyers looking for a generic horizontal dashboard rather than a system that acts
Design partner programme

What the first cohort gets and gives

Two to four IDMs or foundries that operate high-value litho, etch, deposition, CMP or inspection modules and agree to baseline yield, excursion, cycle-time and engineer-load metrics before any recommendation is enabled.

  1. Shadow mode. We connect to the wedge module read-only, observe and measure the baseline. Nothing is written.
  2. Assist mode. The agent recommends recipe moves, dispositions or dispatch and your engineer approves each one. Accuracy and yield, excursion and cycle-time ROI are measured against the signed baseline.
  3. Graduated autonomy. Low-risk APC, defect and metrology loops run inside the qualified window with rollback and OCAP linkage, if the fab is satisfied with the recommendations.
  4. Conversion. The pilot converts to the Module tier and expands module by module. Design partners get written data-rights terms and a say in the roadmap.
Who it is for

Built for the people who run the fab

We have no customer quotes to show yet and will not invent any. These are the three roles in a fab we build for, and the problems they bring to the first meeting.

Fab, Operations or Yield Director

Owns yield, throughput, cycle time, excursion response and cost per wafer.

What this person is dealing with today

  • Reactive process control that lets overlay, uniformity and CMP excursions destroy yield
  • Multi-million-dollar lot scrap from undetected excursions
  • A severe, scarce process and yield engineering shortage that caps the ramp

Process Integration or Module Engineer

Owns litho, etch, deposition, CMP and implant recipes, process windows and APC.

What this person is dealing with today

  • APC, defect, metrology and MES siloed and reactive across the fab
  • Correctables that lag because metrology is sampled
  • Rule-based dispatch and WIP management that inflate cycle time

Yield, Defect or Metrology Engineer

Owns defect classification, metrology, virtual metrology, yield analytics and wafer and lot genealogy.

What this person is dealing with today

  • Manual, engineer-bound defect classification and SEM review drowning in data
  • Metrology bottlenecks and sampling gaps that miss yield-limiting excursions
  • Genealogy stitched by hand across tool, metrology and MES data
Segments

Where fabs start

Logic and foundry, memory, analog and mixed-signal, specialty and compound semiconductor, and new fabs ramping a node. Most fabs pick one module and one wedge, prove the number, then expand.

Advanced logic and foundryLitho-bound, overlay and CD

Advanced logic and foundry

Sub-3 nm, gate-all-around and backside-power nodes where overlay and CD budgets decide yield. Lithera and Vmetra on the litho and etch modules first.

Memory: DRAM, NAND, HBMHigh-volume, 3D complexity

Memory: DRAM, NAND, HBM

High-aspect-ratio etch and deposition uniformity and CMP planarisation on long flows. Vmetra and Scanira where excursions are most expensive.

Analog and mixed-signalMature nodes, long tails

Analog and mixed-signal

Many products, many recipes, few engineers per tool. Virtual metrology and defect disposition to cover more wafers with the same team.

Specialty and compound semiconductorDifferent materials, same loop

Specialty and compound semiconductor

SiC, GaN and photonics fabs with their own defect and uniformity physics. Scanira and Vmetra models trained per process family.

New fabs and node rampsBlind commitments

New fabs and node ramps

Reshored and greenfield capacity ramping under schedule pressure. Fabtwin de-risks the ramp before lots run.

Run timeline · scenario

One scenario run, step by step

Every Waferira run is an ordered, inspectable sequence. This is run_7b2e9c on Module M2 · 300 mm · metal-1 · lot L-48213. Scenario completes in 10 steps with one approval gate. Overlay and CD predicted inside spec, one reticle-repeater signature caught and held for review, dispatch re-optimised, lot released with full genealogy.

run_7b2e9c Module M2 · 300 mm · metal-1 · lot L-48213 illustrative scenario SUCCEEDED
  1. 01 ingest.lot SUCCEEDED 0.7 s

    Fab Orchestrator · Pulled lot L-48213 from fab MES: 25 wafers, 300 mm, metal-1 layer, route, reticle, overlay and CD spec and the standing cycle-time target. Locked the target envelope for the run.

  2. 02 twin.simulate SUCCEEDED 38 s

    Fab Twin · Simulated 64 candidate correctable, recipe and dispatch sets on the as-run fab twin and ranked them on predicted overlay residual, CD uniformity, excursion risk and cycle time.

  3. 03 litho.correctables SUCCEEDED 1 m 20 s

    Litho-and-Overlay · Per-field overlay correctables and a focus-dose trim written to scanner SCN-07 over SECS/GEM after the previous lot's residual trended toward the control limit. Predicted overlay residual back inside spec.

  4. 04 etch.uniformity SUCCEEDED 58 s

    Etch-and-Depo · Chamber B on etcher ETCH-12 showed an edge-fast uniformity drift in FDC. Pressure and RF trims written within the qualified recipe window; predicted CD uniformity recovered.

  5. 05 cmp.removal SUCCEEDED 46 s

    CMP-and-Implant · Downforce and platen-speed trim on CMP-03 against the virtual removal-rate estimate to hold post-CMP thickness and dishing inside the window.

  6. 06 inspect.classify SUCCEEDED continuous

    Defect-and-Inspect · Inline optical, e-beam review and SEM imagery fused at the tool edge. 1,412 events classified, most dispositioned nuisance; one reticle-repeater signature on three dies flagged for review.

  7. 07 vm.score SUCCEEDED 2.1 s

    Metrology-and-Virtual · Virtual metrology scored every wafer at post-etch and post-CMP from tool-sensor and FDC signatures. Two wafers routed to physical metrology on predicted variance; the rest sampled at plan.

  8. 08 approve.human APPROVAL 1 m 04 s

    Fab Orchestrator · The reticle-repeater signature called for a reticle inspection hold and a recipe move outside the qualified window. Held for the module process engineer and approved at 03:14:27.

  9. 09 dispatch.route SUCCEEDED 4.3 s

    Yield-and-Dispatch · Dispatch re-optimised across 1,840 lots in WIP under reticle, chamber and qualification constraints. The lot routed to the qualified chamber with the shortest predicted queue; AMHS move issued to the stocker.

  10. 10 lot.release SUCCEEDED 1 m 05 s

    Quality-and-Conformance · Lot L-48213 moved on: genealogy written (recipe moves, correctables, FDC signatures, VM scores, defect map, approvals) and checked against the layer spec.

Autonomy

Four levels, set per agent and per tool

A fab does not go from manual APC to unattended control in one step. Waferira makes the level explicit, auditable and reversible at any time. The first release runs shadow mode, then assist mode, then graduated autonomy for low-risk APC, defect and metrology loops.

Autonomy levels and the human role at each
LevelWhat the agent doesWhat the human doesWhere it sits in a pilot
L1 · AdvisoryRecommends recipe moves, dispositions and dispatch, with citationsEnters every change manuallyShadow mode, first on the design-partner cell
L2 · SupervisedProposes a recipe write or hold; it executes on approvalApproves each move in the review consoleAssist mode, where accuracy and ROI are proven
L3 · BoundedWrites inside the qualified recipe window, tool-state checks and OCAP linkageApproves holds, out-of-window moves and lot releaseGraduated autonomy for low-risk APC, defect and metrology loops
L4 · Qualified loopsRuns a qualified loop without prompting, inside its envelopeSets the envelope; reviews the shift recordPlanned; reserved for loops the fab has qualified
FAQ

Straight answers

The questions fab directors and process engineers ask in the first meeting.

Yes, over SECS/GEM, but only inside the qualified recipe window for that tool, with per-parameter limits and tool-state checks, and only at the autonomy level your fab has set. Level 1 is advisory: Waferira recommends and an engineer enters everything. Design partners start there, in shadow mode.

Get started

Apply as a design partner

Tell us the module, the metric and the baseline you would sign. We will tell you honestly whether the wedge fits.